1. Technical Field
The present invention relates to a semiconductor memory and more particularly pertains to a sense system for a random access memory (RAM).
2. Background Art
CMOS technology has been applied to DRAM architectures in an effort to enhance memory density while reducing power. In addition, various memory circuit designs have been proposed to improve operation speed and reliability. An example of such a design is the so-called 2/3 VDD bitline precharge sensing scheme disclosed in U.S. Pat. No. 4,816,706 (Japanese Published Unexamined Patent Application (Patent Kokai) No. 64-72395) by S. H. Dhong et al.
With reference to FIG. 4 (Prior Art) the memory circuit of the above-mentioned U.S. patent has a memory sense amplifier circuit comprised of a first latch consisting of cross-coupled N-channel MOS FETs (NMOS FET) 18 and 20 and a second latch consisting of cross-coupled P-channel MOS FETs (PMOS FET) 14 and 16.
A common node 38 of the first latch is connected to ground through an NMOS FET 24 which is controlled by a latching clock .0.s. A common node 36 of the second latch is connected to a power supply voltage VDD through a PMOS FET 22 which is controlled by another latching clock .0.sp. The first and second latch circuits are connected through PMOS FETs 10 and 12 whose gates are grounded. Between bitlines 26 and 28, an equalizing device consisting of a PMOS FET 30 is connected.
At the memory sensing time, the sense amplifier circuit is activated by the latching clocks .0.s and .0.sp, thereby amplifying the potential difference between the bitlines 26 and 28. The voltage of a lower level bitline is pulled down by the first latch, but the downward swing of the bitline voltage is clamped at the absolute value of the threshold voltage (VTP) of the grounded-gate PMOS coupling FETs 10 and 12. The precharging of the bitlines after the sensing operation is made by equalizing the voltages of the bitlines 26 and 28 by means of the PMOS FET 30 (.0..sub.eq). After the sensing operation, the higher level bitline is pulled up from the precharge level to VDD by the second latch, while the lower level bitline remains at the voltage level of VTP. Accordingly, by equalization, the bitlines 26 and 28 are precharged to (VDD+VTP)/2, normally being at 2/3 VDD.
The memory circuit of this patent has the advantage of achieving high speed sensing, while saving power by limiting the voltage swing of the bitlines within a voltage range of (VDD-VTP). A further advantage is that because the downward swing of the bitline voltage is clamped at VTP, the bitline voltage swing is symmetrical relative to the precharge level, even when a 2/3 VDD bitline precharge scheme is used, thereby improving noise immunity. The sensing scheme using the 2/3 VDD bitline precharge system is also described in an article by S. H. Dhong et al. "High-Speed Sensing Scheme for CMOS DRAM'S", IEEE Journal of Solid-State Circuits, Vol. 23, pp. 34-40, Feb., 1988.
However, the PMOS FETs 10 and 12 of the memory circuit of this patent operate in a source-follower mode, thus giving high resistances at low voltages that result in reducing the bitline discharge speed. This results in reducing the access speed (i.e. the speed at which write and restore operations can be carried out). Accordingly, in the 2/3 VDD precharge system, it is desirable to limit the downward voltage swing of the bitlines without reducing memory speed. Furthermore, in order to achieve a high performance DRAM, it is desirable to carry out high speed transfers between the sense amplifier circuit and the I/O dataline. These requirements need to be met with low power consumption and without impairing reliability.
Other technical literature considered to have some relevance to this invention is as follows:
Japanese Published Unexamined Patent Application (Patent Kokai) No.62-165787 discloses a DRAM having a restore circuit and a sense amplifier coupled through barrier FETs for load capacitance isolation. The restore circuit is composed of a latch consisting of PMOS FETs which are cross-coupled, with the cross-coupled nodes connected to a pair of bitlines. The sense amplifier is composed of a latch consisting of NMOS FETs which are cross-coupled. The cross-coupled nodes of the restore circuit and those of the sense amplifier are coupled through barrier transistors consisting of NMOS FETs. To the gate of each barrier FET, a constant voltage that is larger than the summation of the bitline precharge voltage and the threshold voltage of the barrier FET is applied. However, this prior art does not disclose limiting the downward voltage swing of the bitlines by controlling the voltage of the common node of the sense latch and coupling the sense latch to I/O data lines through PMOS FET gates, as in the present invention.
Japanese Published Unexamined Patent Application (Patent Kokai) No. 63-197093 discloses a DRAM having a first sense amplifier consisting of cross-coupled NMOS FETs and a second sense amplifier consisting of cross-coupled PMOS-FETs. The cross-coupled nodes of the first sense amplifier are directly connected with the cross-coupled nodes of the second sense amplifier and are also connected with a pair of bitlines. A precharge voltage generating circuit is connected to the common node of the first sense amplifier. Between the common node of the first sense amplifier and the pair of bitlines, a pair of NMOS FETs are connected which turn on during the precharging period; between the common node of the second sense amplifier and a pair of bitlines, a pair of PMOS FETs are connected which also turn on during the precharging period. When the pair of bitlines are equalized to 1/2 VCC (VCC is the high power supply voltage) by an equalizing FET connected between the pair of bitlines, the precharge voltage generating circuit is also turned on. The precharge voltage generating circuit generates a bitline precharge voltage VBL which is nearly equal to 1/2 VCC, said voltage being coupled to the pair of bitlines and the common node of the second sense amplifier through the pair of NMOS FETs and the pair of PMOS FETs. In this way, the pair of bitlines and the common nodes of both sense amplifiers are reliably precharged to the precharge voltage VBL which is nearly equal to 1/2 VCC. This prior art does not disclose limiting the downward voltage swing of the bitline by controlling the voltage of the common node of the sense latch and coupling the sense latch to I/O data lines through PMOS FET gates, as in the present invention.